Top Verilog repos

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77,942 repos

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RankRepoStarsDeveloper
smunaut/ice40-playground on Github111ice40-playground239smunaut
openasic-org/xkISP on Github112xkISP233openasic-org
vipinkmenon/neuralNetwork on Github113neuralNetwork231vipinkmenon
hamsternz/DisplayPort_Verilog on Github114DisplayPort_Verilog230hamsternz
jotego/jtcores on Github115jtcores229jotego
abdelazeem201/ASIC-Design-Roadmap on Github116ASIC-Design-Roadmap228abdelazeem201
cliffordwolf/SimpleVOut on Github117SimpleVOut228cliffordwolf
funningboy/uvm_axi on Github118uvm_axi228funningboy
budude2/openfpga-GBC on Github119openfpga-GBC225budude2
openasic-org/xk265 on Github120xk265221openasic-org