Verilog

languages / Verilog
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1gravatar for alexforencichalexforencich85,093
2gravatar for ultraembeddedultraembedded333,890
3gravatar for YosysHQYosysHQ83,359
4gravatar for T-head-SemiT-head-Semi53,355
5gravatar for ZipCPUZipCPU353,121
6gravatar for WangXuan95WangXuan95192,685
7gravatar for SI-RISCVSI-RISCV12,514
8gravatar for freecoresfreecores2952,102
9gravatar for darklifedarklife21,885
10gravatar for The-OpenROAD-ProjectThe-OpenROAD-Project71,840
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YosysHQ/picorv32 on Github1picorv322,768YosysHQ
SI-RISCV/e200_opensource on Github2e200_opensource2,514SI-RISCV
alexforencich/verilog-ethernet on Github3verilog-ethernet1,903alexforencich
darklife/darkriscv on Github4darkriscv1,874darklife
T-head-Semi/wujian100_open on Github5wujian100_open1,793T-head-Semi
nvdla/hw on Github6hw1,609nvdla
corundum/corundum on Github7corundum1,459corundum
pConst/basic_verilog on Github8basic_verilog1,426pConst
analogdevicesinc/hdl on Github9hdl1,376analogdevicesinc
The-OpenROAD-Project/OpenROAD on Github10OpenROAD1,322The-OpenROAD-Project
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