Verilog

languages / Verilog
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1gravatar for alexforencichalexforencich83,877
2gravatar for ultraembeddedultraembedded332,984
3gravatar for T-head-SemiT-head-Semi52,944
4gravatar for YosysHQYosysHQ82,867
5gravatar for ZipCPUZipCPU362,669
6gravatar for SI-RISCVSI-RISCV12,301
7gravatar for The-OpenROAD-ProjectThe-OpenROAD-Project72,150
8gravatar for freecoresfreecores2951,764
9gravatar for darklifedarklife11,627
10gravatar for nvdlanvdla21,464
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YosysHQ/picorv32 on Github1picorv322,419YosysHQ
SI-RISCV/e200_opensource on Github2e200_opensource2,301SI-RISCV
T-head-Semi/wujian100_open on Github3wujian100_open1,711T-head-Semi
darklife/darkriscv on Github4darkriscv1,627darklife
alexforencich/verilog-ethernet on Github5verilog-ethernet1,500alexforencich
nvdla/hw on Github6hw1,451nvdla
analogdevicesinc/hdl on Github7hdl1,166analogdevicesinc
corundum/corundum on Github8corundum1,158corundum
pConst/basic_verilog on Github9basic_verilog1,156pConst
ZipCPU/zipcpu on Github10zipcpu1,039ZipCPU
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